This invention relates to an architecture for ABR (available bit rate) processing within a packet based switch such as an ATM (asynchronous transfer mode) switch.
Traditional packet switch (or ATM switch) architectures are costly to maintain and upgrade because they tend to couple components that implement unrelated functions. Coupling of components occurs when their designs are highly interdependent on each other, such that one component cannot be changed without also changing the other component.
One example of coupling is the incorporation of one or more embedded computing systems into the platform on which switching takes place. This feature is undesirable because it couples the computing system, which implements software control functions, with other components that implement unrelated functions such as routing and automatic parameter control. Tight coupling between the embedded computing system and the other components on the switch means that the computing system cannot be changed without also changing all the other components on the switch. Because the embedded computing systems require upgrades far more often than other components on the switch, this feature drives-up maintenance and upgrade costs, and is therefore undesirable. Known ATM switch architectures address this problem by moving software control functions, and any embedded computing systems, off the switching platform to standard computing platforms such as workstations. In such architectures, the platform holding the rest of the switching platform is referred to as a switching element (SE), while the platform holding the decoupled computing system is hereinafter referred to as a computing unit (CU). The use of a CU and SE connected only by a high-speed ATM link enforces a strict interface between the two that allows for the CU to be upgraded and scaled independently of the components comprising the SE.
Another example of coupling is the implementation of cell processing functions on the same printed circuit boards that implement line interface functions. This feature has been recognized to be a drawback because it couples the components that implement line interface functions, which do not change often, to the components that implement cell processing functions, which are in a relative state of continual flux. Known ATM switch architectures address this problem by centralizing the components that implement cell processing functions, into cell processing modules. The cell processing modules are separated from the modules containing the line interface components, which are hereinafter referred to as line interface modules, using a well-defined and stable interface.
Yet another example of coupling is the use of function-specific communication channels for connecting components on the SE to each other. As with the other examples of coupling, this coupling inhibits functionally unrelated components that are connected to each other from being upgraded independently of one another. Unlike the other examples of coupling however, correctional adjustments to the ATM switch architecture have yet to be developed in response to this coupling problem.
More specifically, in current ATM switch architectures, the components within the SE are interconnected to one another using a plurality of dedicated unique connections. That is, the number of buses, the width of the buses, the signals used to coordinate transfers, the timing of the buses and other fundamental characteristics vary from connection to connection. Such connections are undesirable because they couple components that are in a constant state of flux to more stable components. It is desirable to protect the investments made in the more stable components by decoupling them from the unstable components. It is preferable that the decoupling be achieved without significantly reducing switching performance.
Partitioning of a switch architecture involves mapping a plurality of functions that need to be performed on the switch, to a plurality of components or modules that can perform those functions. In partitioning a switch architecture, it is often desirable that closely related functions be mapped on to the same component, since such functions tend to have similar context memory requirements. Such mappings optimize the utilization of many switch resources, including the memory.
A particular functionality provided in ATM switches which would benefit from partitioning is the ABR (available bit rate) service. The ABR service in ATM networks is intended to make the best use of remaining capacity after higher priority services such as CBR (constant bit rate) and VBR (variable bit rate) have been provided for. ABR employs a closed-loop flow control mechanism based on RM (resource management) cells to allocate and moderate user access to the available bandwidth. The flow control loop can be end-to-end in which case the RM cells travel all the way from source to destination before being looped back, or it can be segmented into smaller control loops with interim switches emulating the behaviour of the end systems. Such interim switches are referred to as VS/VD (virtual source/virtual destination) switches. The RM cells provide information regarding the congestion level in the switches in the path and regarding the bandwidth allocated to individual sources. This information is used by the source to modify its transmission rate, the objective being to utilize link capacity fully while not losing any cells as a result of congestion. ABR is not intended for real-time applications, and no guarantees are made with respect to cell delay and cell delay variation.
Each RM cell contains an ER (explicit rate) parameter which may be adjusted as the RM cells pass through the switches in the path in either the forward or backward direction. The ER contained in the RM cell when it returns to the source is the maximum rate at which the source can send cells. The ER may be reduced as low as the MCR (minimum cell rate), this being the minimum cell rate guaranteed to the source during connection establishment.
Each RM cell also contains a CI (congestion indication) parameter and an NI (no increase) parameter which may be adjusted as the RM cells pass through the switches in the path in either the forward or backward direction. The CI/NI parameters contained in the RM cell when it returns to the source are used to indicate to the source what type of relative increase or decrease should be effected to the rate at which the source can send cells. More specifically, the source is allowed to send cells at a rate entitled the ACR (allowed cell rate), and it is this ACR which is iteratively adjusted by the source each time it receives a returned RM cell as a function of the CI/NI parameters.
ABR functionality is typically spread across a number of switch components, and is coupled to queueing, scheduling and shaping components among other components. This means that if any aspect of the ABR functionality is to be changed, a large scale redevelopment of many components often needs to be undertaken, and this would be very costly. ABR is still a young technology, and as such it is likely that it will continue to evolve after other components of ATM switches have stabilized. Because of this, it would be highly desirable to have a switch architecture with a decoupled ABR processing system.
It is an object of the invention to develop a new ABR architecture and a new switch architecture that addresses ABR while decoupling components on the switch so that they can be upgraded or otherwise modified independently of one another, preferably without significantly affecting the performance of the switch.
According to a first broad aspect, the invention provides an ABR (available bit rate) processing method for implementation by an APS (ABR processing subsystem) forming part of an ATM (asynchronous transfer mode) switch which assigns an ingress cell an internal connection number and a buffer address in cell memory, the method comprising the steps of: receiving a plurality of cell ingress input messages each containing a respective internal connection number, a buffer address, and an ingress cell; for each cell ingress input message received, outputting a cell ingress output message containing the internal connection number, the buffer address and the ingress cell, and then conditionally performing ingress cell measurements; receiving a plurality of cell egress input messages each containing a respective internal connection number and buffer address; for each cell egress message received, outputting a cell egress output message containing the internal connection number and buffer address, and then conditionally performing egress cell measurements; for each ingress cell received in an ingress cell input message, if the ingress cell contained in one of said ingress input messages is a BRM cell having ER, CI and NI fields, an internal connection number and a buffer address for the BRM cell, then calculating new ER, CI, NI values, and updating these in the BRM cell and outputting a cell ingress output message containing the updated BRM cell, ICN and buffer address for storage in cell memory and subsequent queueing.
According to a second broad asepct, the invention provides a partitioned ATM switch comprising: a TUB (translation, policing and buffering) block; a CM (memory interface) block; an IOM (input/output management) block; a QMS (queueing, shaping and scheduling) block; an APS (Available bit rate processing system) block, the APS comprising one or more ASICs (application specific integrated circuits) for performing the steps of: receiving from the TUB a plurality of cell ingress input messages each containing a respective internal connection number, a buffer address, and the ingress cell; for each cell ingress input message received, outputting a cell ingress output message containing the internal connection number, the buffer address and the ingress cell, and then conditionally performing ingress cell measurements; receiving from the QMS a plurality of cell egress input messages each containing a respective internal connection number and buffer address; for each cell egress message received, outputting to the TUB a cell egress output message containing the internal connection number and buffer address, and then conditionally performing egress cell measurements; for each ingress cell received in an ingress cell input message, if the ingress cell contained in one of said ingress input messages is a BRM cell having ER, CI and NI fields, an internal connection number and a buffer address for the BRM cell, then calculating new ER, CI, NI values, and updating these in the BRM cell and outputting to the CM a cell ingress output message containing the updated BRM cell, ICN and buffer address for storage in cell memory and subsequent queueing by the QMS; wherein the components of the switch are in communication with each other through common buses, and wherein all of said above messages are communicated through said common buses.
According to a third broad aspect, the invention provides an APS (ABR (available bit rate) processing system) for implementing ABR flow control functionality within an ATM (asynchronous transfer mode) switch which receives cells of a first type, these being cells received from a network and destined for a switching fabric and which receives cells of a second type, these being received from the switching fabric and destined for the network, the APS comprising: one or more hardware devices for performing a first subset of the ABR flow control functionality in relation to cells of said first type; one or more hardware devices for performing a second subset of the ABR flow control functionality in relation to cells of said second type; wherein said first subset and said second subset collectively comprise all of the ABR flow control functionality.